A direct-conversion receiver has gained popularity for use in multi-band, multi-standard communication systems. Despite this, the presence of DC offset is typically a problem for this receiver. In this receiver, a programmable gain amplifier is usually used. As the programmable gain amplifier usually provides a large gain, it is possible that a large DC offset can lead to saturation of the amplifier. Furthermore, a large DC offset may also saturate an analog-to-digital converter (ADC) that follows the amplifier. It is also common that a change of the gain of the programmable gain amplifier can lead to a change of the DC offset. It is desirable to minimize the DC offset for an amplifier, especially a programmable gain amplifier.
In the art, DC offset cancellers based on analog circuits have been disclosed in, e.g., US20050110550 and U.S. Pat. No. 7,969,222. Typically, an analog DC offset canceller employs a negative feedback circuit to compensate for an inherent DC offset of a target amplifier. A sensing amplifier is used for performing low-pass filtering in the negative feedback circuit. The presence of an inherent DC offset in the sensing amplifier causes a residual DC offset appeared at an output of the target amplifier. This residual DC offset is random for different integrated-circuit implementations of the analog DC offset canceller. In U.S. Pat. No. 8,260,227, an analog DC offset canceller is disclosed. This canceller is implemented after the gain stage so that the possibility of amplifier saturation is still present.
Digital DC offset cancellers have also been disclosed in the art. In U.S. Pat. No. 7,215,266, a post-amplification digital DC offset canceller is disclosed. Since the cancellation is done by correcting the DC offset after amplification, there is a possibility of amplifier saturation.
U.S. Pat. No. 7,203,476 discloses a hybrid implementation of a DC offset canceller by combining a digital DC offset correction scheme with an analog one. An ADC is required to convert the target amplifier's output for processing by the digital canceller. It increases the chip area consumed in the integrated-circuit implementation. In addition, the offset cancellation algorithm is complicated, thereby further increasing the required chip area. The digital DC offset canceller also has a longer response time than an analog one does in general.
A multi-stage amplifier is of growing importance for realizing a programmable gain amplifier having a wide range of settable gain. There is a need in the art for DC offset cancellers that enables reduction of the residual DC offset for a multi-stage amplifier without the need for an ADC, which is a chip-area-consuming feature.